1. Field of the Invention
The present invention relates to a semiconductor device for protecting a circuit element from an overvoltage.
2. Description of the Related Art
In conventional semiconductor devices, for example, an N-type epitaxial layer is deposited on a P-type semiconductor substrate in order to form an N-channel LDMOS transistor. A P-type diffusion region, which is used as a back gate region, is formed on the epitaxial layer. An N-type diffusion region, which is used as a source region, is formed on the P-type diffusion layer. Moreover, an N-type diffusion layer, which is used as a drain region, is formed on the epitaxial layer. Then, an N-type buried region, which is placed below the drain region, is formed across the semiconductor substrate and the epitaxial layer. At this time, a breakdown voltage of a PN junction region, which is formed of the buried region and the semiconductor substrate, is set to be lower than a breakdown voltage between the source and the drain of the LDMOS transistor. Even when an overvoltage by which the LDMOS transistor is destroyed is applied to a drain electrode, the PN junction formed of the buried region and the semiconductor substrate breaks down by this structure. As a result, it is possible to prevent the LDMOS transistor from being destroyed by the overvoltage. This technology is described in Published Japanese Patent Translations of PCT International Publications for Patent Applications No. 10-506503 (pages 4 to 5, 7, and FIGS. 1 to 2).
As mentioned above, in the conventional semiconductor devices, the N type buried region is formed below the drain region in order to prevent the LDMOS transistor from being destroyed by the overvoltage applied to the drain region. The N-type buried region is formed to have substantially an equal width to that of the drain region. This structure causes a breakdown current to concentrate on the PN junction region of the N-type buried region and the P-type semiconductor substrate when the overvoltage is applied to the drain region and the PN junction breaks down. This leads to a problem in which the PN junction region is destroyed by a current concentration and heat caused by the concentration.
Moreover, in the conventional semiconductor device, the N-type buried region is formed in a wide range in order to make it possible to prevent the current concentration on the PN junction region. The conventional semiconductor devices here aim to improve a withstand voltage characteristic using a known RESURF principle. For this reason, the N-type buried region is largely formed so as to extend to an isolation region. While, the N-type buried region is formed additionally in the LDMOS transistor in order to form the PN junction region. Namely, when the N-type buried region is formed in the wide range, a space between the drain region and the isolation region is increased to expand an ineffective region where no element is formed. This causes a problem in which an element forming region cannot be efficiently formed with respect to a chip size.
Furthermore, in the conventional semiconductor devices, the P-type semiconductor substrate is used and the PN junction region is formed of the N-type buried region and the P-type semiconductor substrate. This structure causes the overvoltage to be applied to the drain region, so that a generating breakdown current flows to the semiconductor substrate. Accordingly, for example, the breakdown current flows thereto, thereby an electric potential of the semiconductor substrate set in a ground state is increased. In other words, since the semiconductor substrate is used as a flow path for the breakdown current, there are problems in which other elements formed on the same substrate cause an erroneous operation by the increase in the substrate potential and a latch-up phenomenon occurs.